yet another list of MOS Technology 6502 opcodes
This page contains lists of documented instructions and opcodes of the 8bit MOS Technology 6502 CPU (basic model only; not the 65C02 etc.).
I copied this information manually from the scanned book Programming the 65816 (download the PDF here or here). I used the version that had its pages as images because there were errors in the OCRâ€™d version (see comments at NESDev Wiki). Other sources: Wikipedia, NESDev Wiki.
instructions
There are 56 instructions (threeletter mnemonics):
adc
, and
, asl
, bcc
, bcs
, beq
, bit
, bmi
, bne
, bpl
, brk
, bvc
, bvs
, clc
, cld
, cli
, clv
, cmp
, cpx
, cpy
, dec
, dex
, dey
, eor
, inc
, inx
, iny
, jmp
, jsr
, lda
, ldx
, ldy
, lsr
, nop
, ora
, pha
, php
, pla
, plp
, rol
, ror
, rti
, rts
, sbc
, sec
, sed
, sei
, sta
, stx
, sty
, tax
, tay
, tsx
, txa
, txs
, tya
addressing modes
name used on this page  official name 

(abs) 
Absolute Indirect 
(zp),y 
Zero Page Indirect Indexed with Y (Postindexed) 
(zp,x) 
Zero Page Indexed Indirect with X (Preindexed) 
abs 
Absolute 
abs,x 
Absolute Indexed with X 
abs,y 
Absolute Indexed with Y 
acc 
Accumulator 
imm 
Immediate 
imp 
Implied 
rel 
Program Counter Relative 
zp 
Zero Page 
zp,x 
Zero Page Indexed with X 
zp,y 
Zero Page Indexed with Y 
Note: on this page, Implied (imp
) denotes any operandless addressing mode (except acc
in some assemblers).
See also page 34 of Programming the 65816.
instructions and addressing modes by opcode
Rows denote first digits of hexadecimal opcodes. Columns denote last digits of hexadecimal opcodes. To look up e.g. A9
, see row A_
and column _9
.
_0 
_1 
_2 
_3 
_4 
_5 
_6 
_7 
_8 
_9 
_A 
_B 
_C 
_D 
_E 
_F 


0_ 
brk imp 
ora (zp,x) 
ora zp 
asl zp 
php imp 
ora imm 
asl acc 
ora abs 
asl abs 

1_ 
bpl rel 
ora (zp),y 
ora zp,x 
asl zp,x 
clc imp 
ora abs,y 
ora abs,x 
asl abs,x 

2_ 
jsr abs 
and (zp,x) 
bit zp 
and zp 
rol zp 
plp imp 
and imm 
rol acc 
bit abs 
and abs 
rol abs 

3_ 
bmi rel 
and (zp),y 
and zp,x 
rol zp,x 
sec imp 
and abs,y 
and abs,x 
rol abs,x 

4_ 
rti imp 
eor (zp,x) 
eor zp 
lsr zp 
pha imp 
eor imm 
lsr acc 
jmp abs 
eor abs 
lsr abs 

5_ 
bvc rel 
eor (zp),y 
eor zp,x 
lsr zp,x 
cli imp 
eor abs,y 
eor abs,x 
lsr abs,x 

6_ 
rts imp 
adc (zp,x) 
adc zp 
ror zp 
pla imp 
adc imm 
ror acc 
jmp (abs) 
adc abs 
ror abs 

7_ 
bvs rel 
adc (zp),y 
adc zp,x 
ror zp,x 
sei imp 
adc abs,y 
adc abs,x 
ror abs,x 

8_ 
sta (zp,x) 
sty zp 
sta zp 
stx zp 
dey imp 
txa imp 
sty abs 
sta abs 
stx abs 

9_ 
bcc rel 
sta (zp),y 
sty zp,x 
sta zp,x 
stx zp,y 
tya imp 
sta abs,y 
txs imp 
sta abs,x 

A_ 
ldy imm 
lda (zp,x) 
ldx imm 
ldy zp 
lda zp 
ldx zp 
tay imp 
lda imm 
tax imp 
ldy abs 
lda abs 
ldx abs 

B_ 
bcs rel 
lda (zp),y 
ldy zp,x 
lda zp,x 
ldx zp,y 
clv imp 
lda abs,y 
tsx imp 
ldy abs,x 
lda abs,x 
ldx abs,y 

C_ 
cpy imm 
cmp (zp,x) 
cpy zp 
cmp zp 
dec zp 
iny imp 
cmp imm 
dex imp 
cpy abs 
cmp abs 
dec abs 

D_ 
bne rel 
cmp (zp),y 
cmp zp,x 
dec zp,x 
cld imp 
cmp abs,y 
cmp abs,x 
dec abs,x 

E_ 
cpx imm 
sbc (zp,x) 
cpx zp 
sbc zp 
inc zp 
inx imp 
sbc imm 
nop imp 
cpx abs 
sbc abs 
inc abs 

F_ 
beq rel 
sbc (zp),y 
sbc zp,x 
inc zp,x 
sed imp 
sbc abs,y 
sbc abs,x 
inc abs,x 
opcodes by instruction and addressing mode
There are 151 opcodes (combinations of instruction and addressing mode).
(abs) 
(zp),y 
(zp,x) 
abs 
abs,x 
abs,y 
acc 
imm 
imp 
rel 
zp 
zp,x 
zp,y 


adc 
71 
61 
6D 
7D 
79 
69 
65 
75 

and 
31 
21 
2D 
3D 
39 
29 
25 
35 

asl 
0E 
1E 
0A 
06 
16 

bcc 
90 

bcs 
B0 

beq 
F0 

bit 
2C 
24 

bmi 
30 

bne 
D0 

bpl 
10 

brk 
00 

bvc 
50 

bvs 
70 

clc 
18 

cld 
D8 

cli 
58 

clv 
B8 

cmp 
D1 
C1 
CD 
DD 
D9 
C9 
C5 
D5 

cpx 
EC 
E0 
E4 

cpy 
CC 
C0 
C4 

dec 
CE 
DE 
C6 
D6 

dex 
CA 

dey 
88 

eor 
51 
41 
4D 
5D 
59 
49 
45 
55 

inc 
EE 
FE 
E6 
F6 

inx 
E8 

iny 
C8 

jmp 
6C 
4C 

jsr 
20 

lda 
B1 
A1 
AD 
BD 
B9 
A9 
A5 
B5 

ldx 
AE 
BE 
A2 
A6 
B6 

ldy 
AC 
BC 
A0 
A4 
B4 

lsr 
4E 
5E 
4A 
46 
56 

nop 
EA 

ora 
11 
01 
0D 
1D 
19 
09 
05 
15 

pha 
48 

php 
08 

pla 
68 

plp 
28 

rol 
2E 
3E 
2A 
26 
36 

ror 
6E 
7E 
6A 
66 
76 

rti 
40 

rts 
60 

sbc 
F1 
E1 
ED 
FD 
F9 
E9 
E5 
F5 

sec 
38 

sed 
F8 

sei 
78 

sta 
91 
81 
8D 
9D 
99 
85 
95 

stx 
8E 
86 
96 

sty 
8C 
84 
94 

tax 
AA 

tay 
A8 

tsx 
BA 

txa 
8A 

txs 
9A 

tya 
98 
CPU cycle counts by instruction and addressing mode
Notes:
 * = add one cycle if page boundary is crossed
 ** = add one cycle if branch is taken to same page, or two cycles if branch is taken to different page
(abs) 
(zp),y 
(zp,x) 
abs 
abs,x 
abs,y 
acc 
imm 
imp 
rel 
zp 
zp,x 
zp,y 


adc 
5*  6  4  4*  4*  2  3  4  
and 
5*  6  4  4*  4*  2  3  4  
asl 
6  7  2  5  6  
bcc 
2**  
bcs 
2**  
beq 
2**  
bit 
4  3  
bmi 
2**  
bne 
2**  
bpl 
2**  
brk 
7  
bvc 
2**  
bvs 
2**  
clc 
2  
cld 
2  
cli 
2  
clv 
2  
cmp 
5*  6  4  4*  4*  2  3  4  
cpx 
4  2  3  
cpy 
4  2  3  
dec 
6  7  5  6  
dex 
2  
dey 
2  
eor 
5*  6  4  4*  4*  2  3  4  
inc 
6  7  5  6  
inx 
2  
iny 
2  
jmp 
5  3  
jsr 
6  
lda 
5*  6  4  4*  4*  2  3  4  
ldx 
4  4*  2  3  4  
ldy 
4  4*  2  3  4  
lsr 
6  7  2  5  6  
nop 
2  
ora 
5*  6  4  4*  4*  2  3  4  
pha 
3  
php 
3  
pla 
4  
plp 
4  
rol 
6  7  2  5  6  
ror 
6  7  2  5  6  
rti 
6  
rts 
6  
sbc 
5*  6  4  4*  4*  2  3  4  
sec 
2  
sed 
2  
sei 
2  
sta 
6  6  4  5  5  3  4  
stx 
4  3  4  
sty 
4  3  4  
tax 
2  
tay 
2  
tsx 
2  
txa 
2  
txs 
2  
tya 
2 
download as PDF
all instructions, addressing modes, opcodes and CPU cycle counts on a singlepage A4 PDF (42 kB)