Yet another list of MOS Technology 6502 opcodes

This page contains lists of documented instructions and opcodes of the 8-bit MOS Technology 6502 CPU (basic model only; not the 65C02 etc.).

I copied this information manually from the scanned book Programming the 65816 (download the PDF here or here). I used the version that had its pages as images because there were errors in the OCR'd version (see comments at NESDev Wiki). Other sources: Wikipedia, NESDev Wiki.

Table of contents

Instructions

instruction official name affected by flags flags affected
adc Add With Carry C, D N, Z, C, V
and And Accumulator With Memory N, Z
asl Shift Memory or Accumulator Left N, Z, C
bcc Branch if Carry Clear C
bcs Branch if Carry Set C
beq Branch if Equal Z
bit Test Memory Bits against Accumulator N, Z, V
bmi Branch if Minus N
bne Branch if Not Equal Z
bpl Branch if Plus N
brk Software Break I
bvc Branch if Overflow Clear V
bvs Branch if Overflow Set V
clc Clear Carry Flag C
cld Clear Decimal Mode Flag D
cli Clear Interrupt Disable Flag I
clv Clear Overflow Flag V
cmp Compare Accumulator with Memory N, Z, C
cpx Compare Index Register X with Memory N, Z, C
cpy Compare Index Register Y with Memory N, Z, C
dec Decrement N, Z
dex Decrement Index Register X N, Z
dey Decrement Index Register Y N, Z
eor Exclusive-OR Accumulator with Memory N, Z
inc Increment N, Z
inx Increment Index Register X N, Z
iny Increment Index Register Y N, Z
jmp Jump
jsr Jump to Subroutine
lda Load Accumulator from Memory N, Z
ldx Load Index Register X from Memory N, Z
ldy Load Index Register Y from Memory N, Z
lsr Logical Shift Memory or Accumulator Right N, Z, C
nop No Operation
ora OR Accumulator with Memory N, Z
pha Push Accumulator
php Push Processor Status Register N, Z, C, V, D, I
pla Pull Accumulator N, Z
plp Pull Status Flags N, Z, C, V, D, I
rol Rotate Memory or Accumulator Left C N, Z, C
ror Rotate Memory or Accumulator Right C N, Z, C
rti Return from Interrupt N, Z, C, V, D, I
rts Return from Subroutine
sbc Subtract with Borrow from Accumulator C, D N, Z, C, V
sec Set Carry Flag C
sed Set Decimal Mode Flag D
sei Set Interrupt Disable Flag I
sta Store Accumulator to Memory
stx Store Index Register X to Memory
sty Store Index Register Y to Memory
tax Transfer Accumulator to Index Register X N, Z
tay Transfer Accumulator to Index Register Y N, Z
tsx Transfer Stack Pointer to Index Register X N, Z
txa Transfer Index Register X to Accumulator N, Z
txs Transfer Index Register X to Stack Pointer
tya Transfer Index Register Y to Accumulator N, Z

Addressing modes

name used
on this page
official name example of
syntax
imp Implied inx
acc Accumulator asl a
imm Immediate lda #$FF
zp Direct Page lda $FF
zp,x Direct Page Indexed,X lda $FF,x
zp,y Direct Page Indexed,Y ldx $FF,y
abs Absolute lda $FFFF
abs,x Absolute Indexed,X lda $FFFF,x
abs,y Absolute Indexed,Y lda $FFFF,y
rel Program Counter Relative beq $FFFF
(abs) Absolute Indirect jmp ($FFFF)
(zp,x) Direct Page Indexed Indirect,X lda ($FF,x)
(zp),y Direct Page Indirect Indexed,Y lda ($FF),y

Opcodes by instruction and addressing mode

There are 151 opcodes (combinations of instruction and addressing mode).

instruction imp acc imm zp zp,x zp,y (zp,x) (zp),y rel abs abs,x abs,y (abs)
adc 69 65 75 61 71 6D 7D 79
and 29 25 35 21 31 2D 3D 39
asl 0A 06 16 0E 1E
bcc 90
bcs B0
beq F0
bit 24 2C
bmi 30
bne D0
bpl 10
brk 00
bvc 50
bvs 70
clc 18
cld D8
cli 58
clv B8
cmp C9 C5 D5 C1 D1 CD DD D9
cpx E0 E4 EC
cpy C0 C4 CC
dec C6 D6 CE DE
dex CA
dey 88
eor 49 45 55 41 51 4D 5D 59
inc E6 F6 EE FE
inx E8
iny C8
jmp 4C 6C
jsr 20
lda A9 A5 B5 A1 B1 AD BD B9
ldx A2 A6 B6 AE BE
ldy A0 A4 B4 AC BC
lsr 4A 46 56 4E 5E
nop EA
ora 09 05 15 01 11 0D 1D 19
pha 48
php 08
pla 68
plp 28
rol 2A 26 36 2E 3E
ror 6A 66 76 6E 7E
rti 40
rts 60
sbc E9 E5 F5 E1 F1 ED FD F9
sec 38
sed F8
sei 78
sta 85 95 81 91 8D 9D 99
stx 86 96 8E
sty 84 94 8C
tax AA
tay A8
tsx BA
txa 8A
txs 9A
tya 98

CPU cycles by instruction and addressing mode

Notes:

instruction imp acc imm zp zp,x zp,y (zp,x) (zp),y rel abs abs,x abs,y (abs)
adc 2 3 4 6 5* 4 4* 4*
and 2 3 4 6 5* 4 4* 4*
asl 2 5 6 6 7
bcc 2**
bcs 2**
beq 2**
bit 3 4
bmi 2**
bne 2**
bpl 2**
brk 7
bvc 2**
bvs 2**
clc 2
cld 2
cli 2
clv 2
cmp 2 3 4 6 5* 4 4* 4*
cpx 2 3 4
cpy 2 3 4
dec 5 6 6 7
dex 2
dey 2
eor 2 3 4 6 5* 4 4* 4*
inc 5 6 6 7
inx 2
iny 2
jmp 3 5
jsr 6
lda 2 3 4 6 5* 4 4* 4*
ldx 2 3 4 4 4*
ldy 2 3 4 4 4*
lsr 2 5 6 6 7
nop 2
ora 2 3 4 6 5* 4 4* 4*
pha 3
php 3
pla 4
plp 4
rol 2 5 6 6 7
ror 2 5 6 6 7
rti 6
rts 6
sbc 2 3 4 6 5* 4 4* 4*
sec 2
sed 2
sei 2
sta 3 4 6 6 4 5 5
stx 3 4 4
sty 3 4 4
tax 2
tay 2
tsx 2
txa 2
txs 2
tya 2

Instructions and addressing modes by opcode

Notes:

_0 _1 _2 _4 _5 _6 _8 _9 _A _C _D _E
0_ brk ora
(zp,x)
ora
zp
asl
zp
php ora
imm
asl
acc
ora
abs
asl
abs
1_ bpl
rel
ora
(zp),y
ora
zp,x
asl
zp,x
clc ora
abs,y
ora
abs,x
asl
abs,x
2_ jsr
abs
and
(zp,x)
bit
zp
and
zp
rol
zp
plp and
imm
rol
acc
bit
abs
and
abs
rol
abs
3_ bmi
rel
and
(zp),y
and
zp,x
rol
zp,x
sec and
abs,y
and
abs,x
rol
abs,x
4_ rti eor
(zp,x)
eor
zp
lsr
zp
pha eor
imm
lsr
acc
jmp
abs
eor
abs
lsr
abs
5_ bvc
rel
eor
(zp),y
eor
zp,x
lsr
zp,x
cli eor
abs,y
eor
abs,x
lsr
abs,x
6_ rts adc
(zp,x)
adc
zp
ror
zp
pla adc
imm
ror
acc
jmp
(abs)
adc
abs
ror
abs
7_ bvs
rel
adc
(zp),y
adc
zp,x
ror
zp,x
sei adc
abs,y
adc
abs,x
ror
abs,x
8_ sta
(zp,x)
sty
zp
sta
zp
stx
zp
dey txa sty
abs
sta
abs
stx
abs
9_ bcc
rel
sta
(zp),y
sty
zp,x
sta
zp,x
stx
zp,y
tya sta
abs,y
txs sta
abs,x
A_ ldy
imm
lda
(zp,x)
ldx
imm
ldy
zp
lda
zp
ldx
zp
tay lda
imm
tax ldy
abs
lda
abs
ldx
abs
B_ bcs
rel
lda
(zp),y
ldy
zp,x
lda
zp,x
ldx
zp,y
clv lda
abs,y
tsx ldy
abs,x
lda
abs,x
ldx
abs,y
C_ cpy
imm
cmp
(zp,x)
cpy
zp
cmp
zp
dec
zp
iny cmp
imm
dex cpy
abs
cmp
abs
dec
abs
D_ bne
rel
cmp
(zp),y
cmp
zp,x
dec
zp,x
cld cmp
abs,y
cmp
abs,x
dec
abs,x
E_ cpx
imm
sbc
(zp,x)
cpx
zp
sbc
zp
inc
zp
inx sbc
imm
nop cpx
abs
sbc
abs
inc
abs
F_ beq
rel
sbc
(zp),y
sbc
zp,x
inc
zp,x
sed sbc
abs,y
sbc
abs,x
inc
abs,x

Download as CSV file

You can download the list of opcodes as a CSV file (7-bit ASCII text). Each line contains the following fields separated by semicolons: hexadecimal opcode, instruction, addressing mode, number of CPU cycles. Sample:

00;brk;imp;7
01;ora;(zp,x);6
05;ora;zp;3
...

Back to front page | Last updated: 28 Jan 2017 | qalle at qalle dot net